The present invention relates to a memory system and a memory access method.
A highly integrated memory chip may include bad memory cells which do not perform desired operation due to the variation in the processing accuracy of the individual memory cells (1-bit storage elements) when the memory cells are manufactured.
A measure that has been taken for the manufacturing variation, for example, is to fabricate memory cells in advance, exceeding the number of memory cells that correspond to actually required capacity and to permit the excessive memory cells to replace bad memory cells to thereby enhance yield. Also, a scheme has been used, in which bits in bad memory cells are remedied using error correcting codes (ECCs).
Further, a scheme has been suggested for a read only memory, such as an ROM or a PROM. Specifically, in this scheme, a memory component that stores a bit sequence and an additional memory component are provided to such a read only memory. When a bad memory cell that can only store either one of “0” and “1” dares to store a value that the bad memory cell in question cannot store, values of individual data bits in the bit sequence are inverted and stored, and the additional memory component is permitted to store a value that indicates the fact that the data have been inverted (see, for example, JP-A 2004-31904 (KOKAI)). In reading out the data, reference is made to the value in the additional memory component, and if there is an indication that the data have been inverted at the time of storage, the read data are inverted and used.
In an electrically rewritable memory, such as an MRAM or an ReRAM, which uses a memory cell that can possess two different resistance values, the memory cell is brought into either a high resistance state or a low resistance state, so that data can be stored by having one value been correlated to a logical value “0” and the other value been correlated to a logical value “1”. When the data are read, it is determined whether each of the resistance values corresponds to the logical value “0” or “1” (or “1” or “0”), based on whether or not the resistance value of the memory cell is smaller or larger than a threshold.
If manufacturing variations are great in manufacturing such memories, a memory cell having the resistance values smaller than the threshold is likely to exist irrespective of the low or high resistance state of the memory cell, or contrarily, a memory cell having the resistance values larger than the threshold is likely to exist irrespective of the low or high resistance state of the memory cell. Such memory cells end up with always reading either “0” or “1”, notwithstanding that “0” or “1” is written.
As a measure taken for the manufacturing variations of MRAMs, for example, a technique called “self-referencing reading” has been used. With this technique, data are first read from a memory cell. After that, “1” (or “0”) is written into the same memory cell in order to determine the value that has been read is “0” or “1”. Then, the memory cell is read again to compare the value that has been read this time with the firstly read value and determine whether the firstly read value is “0” or “1”. Then, the resultant value is again written into the memory cell.
Use of the “self-referencing reading” may enable correct reading/writing between “0” and “1” even when the resistance values vary between memory cells. However, this technique requires two readings and two writings for each memory cell, raising a problem that long access time has to be taken.